1. Field of the Invention
The present invention relates to a semiconductor memory including read and write circuits, such as a semiconductor static RAM.
2. Description of the Background Art
FIG. 7 is a circuit diagram of a conventional synchronous semiconductor static memory (referred to hereinafter as an SRAM for simplification). For the purpose of illustration, a read circuit 4 for one memory cell portion 1 is shown as provided in FIG. 7. In practice, memory cells are arranged in the form of a matrix with rows each connected to a word line and columns each connected to a pair of bit lines.
In FIG. 7, the reference character PRC designates a precharge signal, and RD.sub.-- EN designates a read bit line selection signal which is applied to the gates of PMOS gate transistors Pgt.sub.-- 0, pgt.sub.-- 1 connected between a read circuit 4 and a pair of bit lines BIT.sub.-- 0, BIT.sub.-- 1, respectively, to control the conduction/non-conduction of the gate transistors Pgt.sub.-- 0, Pgt.sub.-- 1. A sense signal SENSE controls the active/inactive state of the read circuit (sense amplifier) 4 which in turn detects a potential difference between the pair of bit lines BIT.sub.-- 0 and BIT.sub.-- 1 to provide output data DOUT.
FIG. 8 is a timing chart showing the read operation of the conventional SRAM of FIG. 7. The read operation from the memory cell portion 1 of the SRAM of FIG. 7 is described below with reference to FIG. 8. A power supply potential VDD is represented by "H", and a ground potential GND is represented by "L" hereinafter.
Prior to start of the read operation, the precharge signal PRC remains "L", and a precharge operation is executed in which PMOS transistors Pprc.sub.-- 0 to Pprc.sub.-- 3 are turned on to set the potentials of the pair of bit lines BIT.sub.-- 0, BIT.sub.-- 1 and a pair of read input lines SIN.sub.-- 0, SIN.sub.-- 1 to "H".
The read operation starts at the rising edge of a clock signal CLK to "H". A word line WORD rises to "H" at a time later than the rising edge of the clock signal CLK by the amount of time tw, to place the memory cell portion 1 into a selecting state. This delay is developed since a row decoder (not shown) for controlling word lines decodes a row address signal to select a desired word line.
The read bit line selection signal RD.sub.-- EN falls to "L" at a time later than the rising edge of the clock signal CLK by the amount of time tr (substantially equal to the time tw) to turn on the gate transistors Pgt.sub.-- 0 and Pgt.sub.-- 1 for electrical connection between the pair of bit lines BIT.sub.-- 0, BIT.sub.-- 1 and the read input lines SIN.sub.-- 0, SIN.sub.-- 1 of the read circuit 4 (bit line selecting state). This delay is developed since a column decoder (not shown) for controlling bit lines decodes a column address signal to select a desired bit line. The precharge signal PRC becomes "H" in response to the bit line selection to complete the precharge operation.
A memory cell 10 in the memory cell portion 1 includes inverters 11 and 12 which establish a loop connection. It is assumed that a node NODE.sub.-- 0 at the output. of the inverter 12 is "H", and a node NODE.sub.-- 1 at the output of the inverter 11 is "L".
In this state, when the word line WORD is selected to rise to "H", current flows from the bit line BIT.sub.-- 1 to the node NODE.sub.-- 1 through an NMOS access transistor Nmc.sub.-- 1 in the memory cell portion 1. This reduces the potential of the bit line BIT.sub.-- 1 from "H". In general, a bit line is connected to a multiplicity of memory cells and accordingly has a very large parasitic capacitance, and a memory cell designed to have a minimum size has a very small current driving capability. Thus, the potential drop rate is low during the time the electrical charge on the bit line is discharged only by the current flowing through one memory cell 10, or during the time between the rising edge of the word line WORD and the rising edge of the sense signal SENSE.
Since the node NODE.sub.-- 0 in the memory cell 10 is "H", no current flows to the access transistor Nmc.sub.-- 0, and the bit line BIT.sub.-- 0 is held at "H". The falling edge of the clock signal CLK triggers the sense signal SENSE to rise to "H". This allows a transistor. Nsa.sub.-- 2 in the read circuit 4 to conduct, activating a sense amplifier 20 including a cross-coupled connection of an inverter 21 consisting of a PMOS transistor Psa.sub.-- 0 and an NMOS transistor Nsa.sub.-- 0 and an inverter 22 consisting of a PMOS transistor Psa.sub.-- 1 and an NMOS transistor Nsa.sub.-- 1.
The potential of the bit line BIT.sub.-- 0 is propagated to the read input line SIN.sub.-- 0, and the potential of the bit line BIT.sub.-- 1 is propagated to the read input line SIN.sub.-- 1. The potential of the read input line SIN.sub.-- 0 is slightly higher than the potential of the read input line SIN.sub.-- 1 and, accordingly, the amount of current flowing through the NMOS transistor Nsa.sub.-- 0 of the inverter 21 is slightly greater than the amount of current flowing through the NMOS transistor Nsa.sub.-- 1 of the inverter 22. Then the potential of the read input line SIN.sub.-- 1 becomes lower to increase the amount of current flowing through the NMOS transistor Nsa.sub.-- 0. This is repeated, and finally the NMOS transistor Nsa.sub.-- 0 becomes completely conducting and the NMOS transistor Nsa.sub.-- 1 becomes completely non-conducting. The electrical charge on the read input line SIN.sub.-- 1 is discharged through the NMOS transistors Nsa.sub.-- 0 and Nsa.sub.-- 2 having a high current driving capability. Thus the potential of the bit line BIT.sub.-- 1 (read input line SIN.sub.-- 1) is rapidly reduced to "L". The potential of the read input line SIN.sub.-- 1 is outputted as the output data DOUT to the exterior through an inverter 13.
Since the falling edge of the clock signal CLK inactivates address lines, the word line WORD and bit line selection signal RD.sub.-- EN reach a non-selecting state with a slight delay. The sense signal SENSE and the precharge signal fall to "L" in response to the transition of the bit line selection signal RD.sub.-- EN to the non-selecting state to inactivate the sense amplifier 20. At the same time, the PMOS transistors Pprc.sub.-- 2 and Pprc.sub.-- 3 initialize the pair of read input lines SIN.sub.-- 0 and SIN.sub.-- 1 of the sense amplifier to "H", and the read operation is completed.
The conventional synchronous SRAM constructed as above described presents a drawback to be described below. The sense amplifier 20 in the read circuit 4 has a large gain, and a small potential difference between the pair of read input lines SIN.sub.-- 0 and SIN.sub.-- 1 is amplified to the power supply potential VDD or ground potential GND when outputted.
This results from a positive feedback function, that is, the state in which one of the NMOS transistors Nsa.sub.-- 0 and Nsa.sub.-- 1 carries more current than the other becomes more firmly fixed when the operation of the sense amplifier starts.
The sense amplifier 20 is not permitted to be activated for reasons of the large gain of the sense amplifier 20 before a sufficiently large potential difference is developed between the pair of bit lines (the pair of read input lines). This is because the setting of the active time period of the sense amplifier 20 earlier than necessary might cause the potential difference between the pair of bit lines not to reach a sensible magnitude due to the unbalanced transistor characteristics of the NMOS transistors Nsa.sub.-- 0 and Nsa.sub.-- 1 and noises on the bit lines, resulting in misjudgment at the start of the operation of the sense amplifier.
The misjudgment at the start of the operation of the sense amplifier is not corrected in some midpoint of the operation since the positive feedback function operates to fix the misjudgment. Thus, the sense amplifier 20 is not permitted to be activated before the potential difference between the pair of bit lines reaches a sensible level (about several hundreds of millivolts). A read time period T0 between the start of the SRAM operation and the provision of the output is expressed as: EQU T0=tw+tb1+tb2 (1)
where tw is a time interval between the rising edge of the clock signal CLK and the rising edge of the word line WORD, tb1 is a time interval between the rising edge of the word line and the provision of the potential difference between desired bit lines, and tb2 is a time interval between activating the sense amplifier and the provision of its output.
As above stated, since the electrical charge on the bit line is discharged only by the small current of the memory cell during the time interval tb1, it takes much time for the sense amplifier 20 to increase the potential difference between the pair of bit lines to the sensible level, resulting in low-speed read operation.